This invention relates generally to capacitors and to capacitor formation in semiconductor wafer processing.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area.
The principle way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. This invention concerns three-dimensional cell capacitor constructions and methods of forming the same.
Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void. In another aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure only partially filling in the void to provide a tubular structure. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure.